Microprocessor Interface Design

In order to come up with a reasonably optimized result when designing a hardware interface for a microprocessor or a specialized application, a designer must be quite knowledgeable and constantly keep abreast of new developments. Not only must he master traditional methods used for logic systems but he must also be familiar with a wide range of solutions and a technology which never stops progressing. The CMOS and TTL integrated circuit families include the basic bricks used to build an interface, although prefabricated modules of various sizes may improve the performance/price ratio. Programmable networks (PLD, PAL ®, GAL ®, etc.) are becoming more and more diversified and gate arrays can justifiably be used for smaller and smaller series. When signals work on low frequencies, they can be read or activated by an appropriately programmed microcontroller, which may work out cheaper than wired logic. Therefore, engineers must never stop improving their knowledge and questioning the developing techniques which they learnt to master and which have proved reliable. This book does not only deal with digital circuits, although the basic idea is to interconnect functional blocks only through logic connections. The word interface here really refers to an interface between a microproces.

A useful tool for the designer and a valuable text book for the student. - Communications International

1 Integrated circuit technologies.- 1.1 Electronic elements.- 1.1.1 Passive components.- 1.1.2 Bipolar transistors.- 1.1.3 MOS transistors.- 1.1.4 Diode logic.- 1.1.5 Static and dynamic characteristics.- 1.1.6 Parameter dispersion.- 1.2 Major logic families.- 1.2.1 The “74” family.- 1.2.2 Evolution.- 1.2.3 TTL circuits.- 1.2.4 Open collector and emitter.- 1.2.5 Three-state outputs.- 1.2.6 CMOS circuits.- 1.2.7 Open and three-state CMOS outputs.- 1.2.8 CMOS-TIL compatibility.- 1.3 Other technologies.- 1.3.1 NMOS circuits.- 1.3.2 Dynamic logic.- 1.3.3 ECL circuits.- 1.3.4 GaAs circuits.- 1.3.5 Fluid and optical logic.- 1.3.6 Special interfaces.- 1.4 Implementation.- 1.4.1 Correct working conditions.- 1.4.2 Thyristor effect.- 1.4.3 Electrostatic problems.- 1.5 Physical devices.- 1.5.1 Chips.- 1.5.2 Packages.- 1.5.3 Printed circuits.- 2 Combinational logic.- 2.1 Signals and logic functions.- 2.1.1 Logic signals.- 2.1.2 Positive and negative logic.- 2.1.3 Decomposition of a logic system.- 2.1.4 Logic gates.- 2.1.5 Equivalences.- 2.1.6 Importance of drawing rules.- 2.1.7 Rules for inverting circles.- 2.1.8 Rise and propagation times.- 2.2 Implementing a combinational system.- 2.2.1 Logic expression.- 2.2.2 Implementation using transistors.- 2.2.3 Standard VLSI library.- 2.2.4 Gate arrays.- 2.2.5 The “74” family.- 2.2.6 Programmable logic.- 2.2.7 PROMs.- 2.3 Transformation of logic functions.- 2.3.1 Karnaugh maps.- 2.3.2 Example.- 2.4 Standard combinational circuits.- 2.4.1 Available functions.- 2.5 Simple gates.- 2.5.1 Gate catalogue.- 2.5.2 Exercise.- 2.5.3 Special gates.- 2.6 Special input gates.- 2.6.1 Low charge inputs.- 2.6.2 Hysteresis threshold inputs.- 2.6.3 Available Schmitt trigger gates.- 2.7 Special output gates.- 2.7.1 Buffered outputs.- 2.7.2 Single state outputs.- 2.7.3 Applications of open collector gates.- 2.7.4 Open collector drivers.- 2.7.5 Three-state outputs.- 2.7.6 Bus termination.- 2.7.7 Three-state buffers and drivers.- 2.7.8 Line drivers.- 2.7.9 Analog switches.- 2.8 Switches and encoders.- 2.8.1 Multiplexors.- 2.8.2 Decoders.- 2.8.3 Display decoders.- 2.8.4 Priority encoders.- 2.8.5 Parity generators.- 2.8.6 Error detection and correction.- 2.9 Comparators and arithmetic circuits.- 2.9.1 Parallel comparators.- 2.9.2 Serial comparison.- 2.9.3 Adders.- 2.9.4 Arithmetic and logic units.- 2.9.5 Anticipated report.- 2.9.6 Multipliers.- 2.9.7 Barrel shifters.- 2.9.8 Other circuits.- 3 Sequential logic systems.- 3.1 Asynchronous sequential systems.- 3.1.1 Oscillators.- 3.1.2 Bistable flip-flops.- 3.1.3 Elementary arbiters.- 3.1.4 Metastable states.- 3.1.5 Latches.- 3.1.6 Addressable latches.- 3.1.7 Designing asynchronous systems.- 3.1.8 Static glitches.- 3.1.9 Example.- 3.2 Synchronous flip-flops.- 3.2.1 The clock pulse.- 3.2.2 Note.- 3.2.3 Multi-phase clock.- 3.2.4 D flip-flops.- 3.2.5 Output conventions.- 3.2.6 Working conditions.- 3.2.7 Metastability probability.- 3.2.8 Double synchronization.- 3.2.9 Standard D flip-flops.- 3.2.10 JK flip-flops.- 3.2.11 Standard JK flip-flops.- 3.2.12 Dynamic SR flip-flops.- 3.2.13 T flip-flops.- 3.2.14 Standard T flip-flops.- 3.2.15 Universality of D and JK flip-flops.- 3.2.16 One’s catchers.- 3.2.17 Double flip-flops.- 3.2.18 Pinpointing an operation.- 3.2.19 Cycle samplers.- 3.2.20 Pulse sampler.- 3.3 Synthesis of sequential systems.- 3.3.1 Synthesis of a semi-synchronous system.- 3.3.2 Synthesis of a synchronous system.- 3.3.3 Principles of the method.- 3.3.4 Conclusion.- 3.4 Complex sequential circuits.- 3.4.1 Standard sequential functions.- 3.4.2 Inhibiting the clock.- 3.4.3 Asynchronous and synchronous reset.- 3.4.4 Asynchronous and synchronous loading.- 3.5 Registers.- 3.5.1 Parallel registers and latches.- 3.5.2 Read-back registers.- 3.5.3 Serial-parallel registers.- 3.5.4 Universal registers.- 3.5.5 Case analysis.- 3.6 Counters.- 3.6.1 Asynchronous counters.- 3.6.2 Divide by 2n counter.- 3.6.3 Synchronous counters.- 3.6.4 Programmable dividers.- 3.6.5 Counters with registers.- 3.6.6 Pseudo-random counters.- 3.6.7 Rate multipliers.- 3.7 Delays and pulses.- 3.7.1 Delay lines.- 3.7.2 RC networks delays.- 3.7.3 Quantified delays.- 3.7.4 Analog oscillators.- 3.7.5 Crystal oscillators.- 3.7.6 Monostables.- 3.7.7 Power-up reset.- 3.8 Standardized logic symbols.- 3.8.1 Main standards.- 3.8.2 IEC-617/AIEE-91 standard.- 3.8.3 Drawing conventions.- 4 Memory circuits.- 4.1 Introduction.- 4.2 Read only memories.- 4.2.1 Principles.- 4.2.2 Types of ROMs.- 4.2.4 Standard PROMs.- 4.2.3 Standard EPROMs.- 4.2.5 E2PROMs.- 4.3 Read Write memories.- 4.3.1 Static RAMs.- 4.3.2 Serial memories.- 4.3.3 Dual ported memories.- 4.3.4 Dynamic RAMs.- 4.3.5 Video RAMs.- 4.3.6 FIFO memories.- 4.3.7 LIFO memories.- 4.3.8 Associative memories.- 5 Programmable logic.- 5.1 Regular logic.- 5.1.1 A simple example.- 5.1.2 Solution based on a decoder.- 5.1.3 Completely programmable solution.- 5.1.4 Partially programmable solution.- 5.1.5 PROM logic.- 5.1.6 PLA logic.- 5.2 PLD logic.- 5.2.1 Simple PLDs.- 5.2.2 Simplifying logic equations for PLDs.- 5.2.3 Correcting existing PLDs.- 5.2.4 Application example: 68008 decoder.- 5.2.5 Asynchronous sequential logic.- 5.2.6 Example: boot flip-flop for 68008.- 5.2.7 Three-state output PLDs.- 5.2.8 Application example: resetting the 68000.- 5.3 Registered PLDs.- 5.3.1 Basic structure.- 5.3.2 Binary counter.- 5.3.3 Gray and special counters.- 5.3.4 Independent clocks.- 5.3.5 Tricks.- 5.3.6 Buried registers.- 5.3.7 Macrocells, PLDs and GALs.- 5.3.8 Existing PLDs.- 5.3.9 Future PLDs.- 6 Input-output interfaces.- 6.1 Logic inputs.- 6.1.1 Filtering and galvanic insulation.- 6.1.2 Digital filtering.- 6.1.3 Reading an analog sensor.- 6.1.4 Suppressing contact bounce.- 6.1.5 Grouped inputs.- 6.1.6 Angular encoder.- 6.1.7 Quadrature encoder.- 6.1.8 Analog angular encoder.- 6.2 Analog inputs.- 6.2.1 Operational amplifiers.- 6.2.2 Ideal model.- 6.2.3 Basic schematics.- 6.2.4 Comparators.- 6.2.5 Instrumentation amplifiers.- 6.2.6 A/D converters.- 6.2.7 Serial interface.- 6.2.8 Analog sensors.- 6.2.9 Voltage-frequency conversion.- 6.3 Output interfaces.- 6.3.1 Microcontroller outputs.- 6.3.2 D/A converters.- 6.3.3 Display controllers.- 6.3.4 Power amplifiers.- 6.3.5 Relays.- 6.3.6 Driving motors.- 6.3.7 Proportional control.- 6.3.8 Collectorless motor.- 6.3.9 Step by step motor.- 6.3.10 Regulated power supplies.- 7 Testing circuits.- 7.1 Types of tests.- 7.1.1 Debugging.- 7.1.2 Manufacturing.- 7.1.3 Maintenance.- 7.2 Test aids.- 7.2.1 Logic indicators.- 7.2.2 Oscilloscopes.- 7.2.3 Logic analyzers.- 7.2.4 Function generator.- 7.2.5 Signature analyzers.- 7.2.6 Industrial tester.- 7.3 Test theory.- 7.3.1 Break-downs and reliability.- 7.3.2 Testability.- 7.3.3 Test coverage.- 7.3.4 Test methods.- 7.4 Design for testability.- 7.4.1 Simulation.- 7.4.2 Oblervability.- 7.4.3 Controllability.- 7.4.4 Initial state.- 7.4.5 Test points.- 7.4.6 Multiplexing.- 7.4.7 Scan paths.- 7.4.8 JTAG standard.- 7.4.9 Signature analysis.- 7.5 Debugging prototypes.- 7.5.1 Testing integrated circuits.- 7.5.2 Testing printed circuit boards.- 7.5.3 Special techniques.- 7.5.4 Memory tests.- 7.5.5 Interferences and disturbances.- 7.5.6 Repairing.- 7.5.7 Conclusion.- 8 Design examples.- 8.1 Simple sequencer.- 8.1.1 Pulse generators.- 8.1.2 Solution using decoders.- 8.1.3 Getting rid of glitches.- 8.1.4 Optimized solutions.- 8.1.5 General solution.- 8.2 Frequency divider.- 8.2.1 Rate multipliers.- 8.2.2 Other solutions.- 8.2.3 VLSI implementation.- 8.3 Sequencer for repetitive resets.- 8.3.1 Problem specifications.- 8.3.2 Possible solutions.- 8.3.3 Simplified solutions.- 8.3.4 Complete solution.- 8.3.5 Optimizing.- 8.4 Double buffers.- 8.4.1 Data and options.- 8.4.2 Problem specifications.- 8.4.3 First synchronous solution.- 8.4.4 Second asynchronous solution.- 8.4.5 Purely asynchronous solution.- 8.4.6 Synchronous synthesis.- 8.4.7 Detailed synthesis.- 8.4.8 Quasi synchronous solution.- 8.5 Multiplexing in a microprocessor interface.- 8.5.1 Registers and latches.- 8.5.2 Multiplexers and demultiplexers.- 8.5.3 Demultiplexing outputs.- 8.5.4 Demultiplexing using a shift register.- 8.5.5 Demultiplexing using a decoder or a PAL.- 8.5.6 Demultiplexing using an addressable latch.- 8.5.7 Demultiplexing using a parallel register.- 8.5.8 Multiplexing the inputs.- 8.5.9 Multiplexing using switches.- 8.5.10 Multiplexing using registers.- 8.5.11 Multiplexing using a three-state driver.- 8.5.12 Multiplexing using a matrix.- 8.5.13 Multiplexing input-outputs.- 8.5.14 Scanned keyboards.- 8.5.15 Conclusion.- References.- Appendix: Integrated circuit catalogue.